1. Field of the Invention
The present invention relates to an address buffer and a semiconductor memory device having the same.
2. Description of Related Art
A conventional semiconductor memory device includes an address buffer comprising a normal address buffer unit for buffering addresses received from address pins in normal operation mode and a mode-setting signal buffer unit for buffering mode-setting signals received from the address pins in a mode-setting operational mode.
The conventional address buffer, however, involves a problem that the logic level of the mode-setting signals is transited in response to the logic level transition of the addresses input through the address pins in the normal operational mode, which increases current consumption. That is, the mode-setting signal buffer unit is actually operated during the normal operational mode, thereby undesirably consuming current.
FIG. 1 illustrates a conventional semiconductor memory device. The conventional semiconductor memory device comprises address pins 10-1 to 10-n, command pins 12-1 to 12-3, address buffers 14-1 to 14-n, a chip selection signal (CSB) buffer 16-1, a row address strobe signal (RASB) buffer 16-2, a column address strobe signal (CASB) buffer 16-3, an address decoder 18, a mode-setting register 20, a command decoder 22 and a PCLKR signal generating circuit 24.
The address pins 10-1 to 10-n receive external addresses A1 to An. The command pins 12-1, 12-2 and 12-3 receive command signals CSB, RASB, CASB, respectively. The address buffers 14-1 to 14-n latch the external addresses A1 to An in response to the PCLKR signal and generate buffered mode-setting signals MAB1 to MABn. The address buffers 14-1 to 14-n buffer the external addresses A1 to An in response to the active command ACT and generate buffered addresses AB1 to ABn. The address decoder 18 decodes the buffered addresses AB1 to ABn and generates decoded addresses DAB1 to DABm. The mode-setting register 20 receives the buffered mode-setting signals MAB1 to MABn and outputs mode-setting signals MDAB1-MDABk in response to the mode-setting command MRS.
The CSB buffer 16-1 buffers the chip selection signal CSB and generates a buffered chip selection signal CSBB. The RASB buffer 16-2 buffers the row address strobe signal RASB and generates a buffered row address strobe signal RASBB. The CASB buffer 16-3 buffers a column address strobe signal CASB and generates a buffered column address strobe signal CASBB. The command decoder 22 decodes the buffered command signals CSBB, RASBB, CASBB and generates a mode-setting command MRS, an active command ACT, a pre-charge command PRE and a refresh command REF. The PCLKR signal generating circuit 24 generates the PCLKR signal in response to the buffered row address strobe signal RASBB.
FIG. 2 illustrates a circuit diagram of the address buffer comprising the normal address buffer unit 30 and the mode-setting signal buffer unit 32. The normal address buffer unit 30 comprises inverters I1, I2, I5, I6 and I7, complementary metal oxide semiconductor (CMOS) transmission gates C1 and C2, and a latch L1 comprising inverters I3 and I4. The mode-setting signal buffer unit 32 comprises an inverter I8, a CMOS transmission gate C3, a PMOS transistor P and a latch L2 comprising inverters I9 and I10.
In FIG. 2, references A, AB, MAB, ACT denote an external address externally input, a buffered address, a mode-setting signal and an active command, respectively. The PCLKR signal is a clock signal generated in response to the row address strobe signal RASB of logic xe2x80x9clowxe2x80x9d level. A reference VCCH denotes a voltage that maintains a logic xe2x80x9chighxe2x80x9d level upon power-up and is then transited to a logic xe2x80x9clowxe2x80x9d level.
The inverter I1 inverts the external address A. The CMOS transmission gate C1 is turned on in response to the PCLKR signal of logic xe2x80x9clowxe2x80x9d level, thereby transmitting an output signal of the inverter I1 to the latch L1. The latch L1 latches and inverts an output signal of the CMOS transmission gate C1. The CMOS transmission gate C2 is turned on in response to the active command of a logic xe2x80x9chighxe2x80x9d level, thereby transmitting an output signal of the latch L1. The inverters 16 and 17 buffer an output signal of the CMOS transmission gate C2, thereby generating the buffered address AB.
The inverter I8 inverts the output signal of the latch L1. The CMOS transmission gate C3 is turned on in response to the signal PCLKR of logic xe2x80x9chighxe2x80x9d level, thereby transmitting an output signal of the inverter I8. The PMOS transistor P is turned on in response to the VCCH signal of logic xe2x80x9clowxe2x80x9d level after power-up and when the voltage of a node n equals the power supply voltage. The latch L2 is reset by the PMOS transistor P, thereby generating the mode-setting signal MAB of a logic xe2x80x9clowxe2x80x9d level. Further, the latch L2 generates the mode-setting signal of a logic xe2x80x9clowxe2x80x9d level when a signal of a logic xe2x80x9chighxe2x80x9d level is transmitted from the CMOS transmission gate C3 to the latch L2. Conversely, latch L2 generates the mode-setting signal of logic xe2x80x9chighxe2x80x9d level when a signal of logic xe2x80x9clowxe2x80x9d level is transmitted.
Therefore, in the normal operation mode that the active command ACT, the pre-charge command PRE or the refresh command REF is applied to the semiconductor memory device, the CMOS transmission gate C1 is turned on in response to the PCLKR signal of a logic xe2x80x9clowxe2x80x9d level generated in response to row address strobe signal RASB, so that the external address A is transmitted to the latch L1 via the inverter I1. When the signal PCLKR of the logic xe2x80x9clowxe2x80x9d level is transited to the logic xe2x80x9chighxe2x80x9d level, the CMOS transmission gate C3 is turned on and a signal, i.e., the address A, latched in the latch L1, is transmitted via the inverter I8 and the CMOS transmission gate C3 to the latch L2.
Accordingly, the mode-setting signal MAB is transited from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level along with the logic level transition of the address A during the normal operation mode, thereby causing undesired current consumption.
FIG. 3 is a timing diagram illustrating operation of the address buffer in FIG. 2, wherein the address A is transited from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level.
When the row address strobe signal RASB of a logic xe2x80x9clowxe2x80x9d level and the address A transiting from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level are externally input to the semiconductor memory device at rising edge of a clock signal CLK, the PCLKR signal is generated in response to the row address strobe signal RASB. The CMOS transmission gate C1 transmits the address A to the latch L1 in response to the PCLKR signal of a logic xe2x80x9clowxe2x80x9d level. The CMOS transmission gate C3 transmits the signal output from the latch L1 to the latch L2 in response to the PCLKR signal of a logic xe2x80x9chighxe2x80x9d level. Accordingly, current is consumed by the address buffer because the mode-setting signal MAB is transited from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level along with level transition of the address A in the normal operation mode. Further, if the active command ACT of a logic xe2x80x9chighxe2x80x9d level is generated, the CMOS transmission gate C2 is turned on and generates the buffered address AB rising up from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level.
Worse, such current consumption by the mode-setting signal buffer unit increases as the number of the address buffers increases.
To overcome the problems described above, a preferred embodiment of the present invention provides an address buffer wherein a mode-setting signal is not changed in response to logic level of an address externally input during a normal operation mode, thereby reducing current consumption, and a semiconductor memory device utilizing such an address buffer.
In accordance with one aspect of the present invention, there is provided an address buffer comprising: a first buffering means for generating a buffered address upon buffering a signal externally applied in a normal operation mode; and a second buffering means for keeping a mode-setting signal in a reset status in the normal operation mode and for generating the mode-setting signal by buffering the signal externally applied in a mode-setting operation mode.
The first address buffer includes: a first transmission gate for transmitting the signal by being turned on in response to a first control signal; a first latch for latching an output signal of the first transmission gate; a second transmission gate for transmitting an output signal of the first latch by being turned on in response to a second control signal; and a buffer for generating the buffered address by buffering an output signal of the second transmission gate.
The second buffer includes: an ANDing circuit for ANDing the first control signal and the mode-setting command; a third transmission gate for transmitting the output signal of the first latch in response to an output signal of the ANDing circuit; and a second latch for generating the mode-setting signal by latching an output signal of the third transmission gate and resetting the mode-setting signal.
The second latch further includes a reset transistor for resetting the mode-setting signal.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of pins; and a plurality of buffers for buffering signals input through the plurality of pins, wherein each of the buffers includes: a first buffering means for generating a buffered signal by buffering the signals in a normal operation mode; and a second buffering means for maintaining a mode-setting signal in a reset status in the normal operation mode and generating the mode-setting signal by buffering the signals in a mode-setting operation mode.
In accordance with further another aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of pins; and a plurality of buffers for buffering signals input through the plurality of pins, wherein each of the buffer includes: a first buffering means for latching the signals in response to a first control signal in a normal operation mode of the semiconductor memory device and generating buffered signals by buffering latched signals in response to a second control signal; a second buffering means for generating a mode-setting signal using the latched signals in response to the first control signal and a mode-setting command in a mode-setting operation mode, and maintaining the mode-setting signal in reset status in the normal operation mode.